1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a nonvolatile semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device is a storage device that can read stored data when required. Semiconductor memory devices may be generally classified into RAM (Random Access Memory) and ROM (Read Only Memory) devices. RAM is typically a volatile memory device, i.e., stored information is lost when power is removed, whereas ROM is typically a nonvolatile memory device, i.e., stored information is retained even when power is removed. Nonvolatile memory devices include, e.g., PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), flash memory devices, etc.
A flash memory device may be a nonvolatile memory device in which data may not be erased even if the power supply is interrupted. A flash memory device may include a unit cell having a stacked structure of a floating gate and a control gate.
Due to the rapid progress of highly integrated nonvolatile memory devices, a method of forming a self-aligned floating gate using a device isolation layer has been widely employed to prevent misalignment of the floating gate. Typically, the method of forming the self-aligned floating gate includes forming the floating gate on active regions, which may be divided by self alignment of a device isolation layer that protrudes toward the upper portion of an exposed substrate.
Also, as the design rule decreases, the trench width of an element isolation region may decrease while the slope thereof increases. As a result, voids may occur when the device isolation layer is formed. In order to overcome this problem, an oxide layer having gap-filling characteristics has been used as a device isolation layer.
However, since the oxide layer may be chemically etched by, e.g., an etchant, during the manufacturing process of the semiconductor, it may become difficult to form the floating gate by self-alignment. In addition, since the lower width of floating gate forming regions, which may be divided by the device isolation layer to form the self-aligned floating gate, may be wider than the upper width of the floating gate forming regions, seams and voids may be generated when the floating gate is formed. For this reason, the characteristics of the semiconductor memory device may frequently deteriorate.